In recent years, remarkable progress has been made in reducing the size and price of electronic appliances incorporating semiconductor integrated circuit devices (hereinafter referred to as “semiconductor devices”), and the demand for reducing the size and price of semiconductor devices has become stronger.
Conventionally, a semiconductor device is provided in a state in which a semiconductor chip and leads for forming external terminals are electrically connected by bonding wires and are encapsulated in a resin or a ceramic. The semiconductor device provided in such a state is mounted on a circuit board. However, a method of mounting on a circuit board a semiconductor chip as it is after being cut out from a semiconductor wafer is becoming a main stream because of the demand for reducing the size of electronic appliances. There is a strong demand for assuring the desired quality of such a semiconductor chip (bare chip) and providing the semiconductor chip at a low price.
Assurance of the quality of semiconductor chips requires a test such as a burn-in test of the semiconductor chips in a wafer state, i.e., semiconductor integrated circuit devices formed on a wafer. In this test, it is impractical, in terms of time and in terms of cost, to test the plurality of semiconductor integrated circuit devices on the wafer one by one or to perform rounds of tests of separated groups of the semiconductor integrated circuit devices each consisting of several ones of the circuit units. A wafer level test method for all of a plurality of semiconductor integrated circuit devices on a wafer by a burn-in test or the like has therefore been developed.
A wafer level test of all semiconductor integrated circuit devices on a wafer requires operating the semiconductor integrated circuit devices by simultaneously applying power supply voltages and signals to electrodes of the semiconductor integrated circuit devices. This test requires the provision of a probe card having a large number of (ordinarily, several ten thousands of) contactors capable of contacting the electrodes of all the semiconductor integrated circuit devices on the wafer. As this probe card, the conventional needle-type probe card, i.e., a type of probe card on which probe needles are arrayed, is not adaptable in terms of number of pins and in terms of price. By considering this, a method has been proposed in which a multiplicity of bumps are formed on a probe card to be used as probe electrodes (see, for example, Japanese Patent Laid-Open No. 7-231019).
In bringing a multiplicity of bumps of a probe card into contact with a multiplicity of corresponding electrodes on a wafer with reliability, there is a need to accurately position (align) the probe card and the wafer while observing the placement of the bumps. Ordinarily, this positioning is performed by relatively moving the wafer while referring to the bumps on the probe card fixed on a particular portion of an alignment apparatus through image processing in a recognition device. A method has also been proposed in which alignment marks such as openings are added to a probe card to be used as a contact-position reference (see, for example, Japanese Patent Laid-Open No. 11-154694).
However, a positional deviation of bumps formed on a probe card occurs easily due to a variation caused at the time of manufacture or a thermal cycle during characteristic inspection. The alignment method using bumps as a reference, therefore, entails a possibility of failure to achieve accurate contact due to a positional deviation of the bumps used as a reference. Since the size of the bumps are extremely small, image processing in a recognition device is considerably difficult to perform and there is a possibility of occurrence of an error in image processing.
In the alignment method using special alignment marks, the alignment marks are added after the formation of bumps by considering the position accuracy of the bumps. However, this method is capable of coping only with the problem relating to the position accuracy at the time of manufacture of a probe card and is incapable of coping with, for example, a change due to a thermal cycle after manufacture of the probe card. Since the alignment marks are formed not simultaneously with the formation of the bumps, there is a possibility of occurrence of an accuracy error with respect to the positions of the bumps in the alignment mark addition step.